• In a computer using the Harvard architecture, the CPU can both read an instruction and perform a data memory access at the same time,[3] even without a cache.

• Even in these cases, it is common to employ special instructions in order to access program memory as though it were data for read-only tables, or for reprogramming; those
  processors are modified Harvard architecture processors.

• • Microcontrollers are characterized by having small amounts of program (flash memory) and data (SRAM) memory, and take advantage of the Harvard architecture to speed processing
  by concurrent instruction and data access.

• If, for instance, every instruction run in the CPU requires an access to memory, the computer gains nothing for increased CPU speed—a problem referred to as being memory bound.

• The solution is to provide a small amount of very fast memory known as a CPU cache which holds recently accessed data.

• A Harvard architecture computer can thus be faster for a given circuit complexity because instruction fetches and data access do not contend for a single memory pathway.

• The separate storage means the program and data memories may feature different bit widths, for example using 16-bit-wide instructions and 8-bit-wide data.

• In the case of a cache miss, however, the data is retrieved from the main memory, which is not formally divided into separate instruction and data sections, although it may
  well have separate memory controllers used for concurrent access to RAM, ROM and (NOR) flash memory.

• Modern uses of the Harvard architecture The principal advantage of the pure Harvard architecture—simultaneous access to more than one memory system—has been reduced by modified
  Harvard processors using modern CPU cache systems.

• Thus, while a von Neumann architecture is visible in some contexts, such as when data and code come through the same memory controller, the hardware implementation gains the
  efficiencies of the Harvard architecture for cache accesses and at least some main memory accesses.

• Modern processors appear to the user to be systems with von Neumann architectures, with the program code stored in the same main memory as the data.

• Relatively pure Harvard architecture machines are used mostly in applications where trade-offs, like the cost and power savings from omitting caches, outweigh the programming
  penalties from featuring distinct code and data address spaces.

• This allows constant data, such as text strings or function tables, to be accessed without first having to be copied into data memory, preserving scarce (and power-hungry)
  data memory for read/write variables.

• The von Neumann nature of memory is then visible when instructions are written as data by the CPU and software must ensure that the caches (data and instruction) and write
  buffer are synchronized before trying to execute those just-written instructions.

• As long as the data that the CPU needs is in the cache, the performance is much higher than it is when the CPU has to get the data from the main memory.

• Contrast with modified Harvard architecture[edit] Main article: Modified Harvard architecture A modified Harvard architecture machine is very much like a Harvard architecture
  machine, but it relaxes the strict separation between instruction and data while still letting the CPU concurrently access two (or more) memory buses.

• For performance reasons, internally and largely invisible to the user, most designs have separate processor caches for the instructions and data, with separate pathways into
  the processor for each.

• Also, a Harvard architecture machine has distinct code and data address spaces: instruction address zero is not the same as data address zero.

• In some systems, instructions for pre-programmed tasks can be stored in read-only memory while data memory generally requires read-write memory.

• In some systems, there is much more instruction memory than data memory so instruction addresses are wider than data addresses.

 

Works Cited

[‘The IAP lines of 8051-compatible microcontrollers from STC have dual ported Flash memory, with one of the two ports hooked to the instruction bus of the processor core, and the other port made available in the special function register region.
2. ^
As in a well described case of Intel 80486.[4]: 26–34 [5]
b. Pawson, Richard (30 September 2022). “The Myth of the Harvard Architecture”. IEEE Annals of the History of Computing. 44 (3): 59–69. doi:10.1109/MAHC.2022.3175612. S2CID 252018052.
c. ^
“Kalimba DSP: User guide” (PDF). July 2006. p. 18. Retrieved 2022-09-23. this is a three-bank Harvard architecture.
d. ^ “386 vs. 030: the Crowded Fast Lane”. Dr. Dobb’s Journal, January 1988.
e. ^ Brown, John Forrest (1994). Embedded systems
programming in C and Assembly. New York: Van Nostrand Reinhold. ISBN 0-442-01817-7. OCLC 28966593.
f. ^ “Embedded Systems Programming: Perils of the PC Cache”. users.ece.cmu.edu. Archived from the original on January 15, 2020. Retrieved 2022-05-26.

Photo credit: https://www.flickr.com/photos/dalecruse/8520482921/’]